----------------------------------------------------------------------------------
-- Company:       Digilent Ro
-- Engineer:      Tudor Armand Ciuleanu
-- 
-- Create Date:   18:10:04 01/12/2008 
-- Module Name:   PWM - Behavioral 
-- Project Name: 	PWM Reference Design	
-- Target Devices: 
-- Tool versions: Xilinx ISE 9.2i
-- Description: Generates a PWM wave on pwm_out output using a 50 MHz input 
-- clock and a switch signal.
--
-- Dependencies: 
--
-- Revision: 0.01 - File Created
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity PWM is
  Port (
    ck      : in  STD_LOGIC; 		--clock input
    cmpPwm  : in  STD_LOGIC_VECTOR(7 downto 0); 	--switch input
    pwm_out : out STD_LOGIC	   --pwm_out output
  );
end PWM;

architecture Behavioral of PWM is

  constant ckPwmRange: integer:= 1;
  -- LSB in the cntPwm alias of cntDiv
  signal cntPwm: unsigned(ckPwmRange+7 downto 0):=(others=>'0');
  -- the superior 8 bits are used for PW Modulator:
  -- cntPwm counts 50MHz/2^ckPwmRange

begin

  PwmCounter: process
  begin
    wait until ck'event and ck='1';
    cntPwm <= cntPwm + 1;
  end process;

  PWM: process(cntPwm, cmpPwm)  -- modulo de logica combinacional
  begin
    if cntPwm(ckPwmRange+7 downto ckPwmRange) <= UNSIGNED(cmpPwm) then
    -- counter value less than reference
      pwm_out <= '1';          -- Output HIGH
    else 
    -- counter value greater than reference
      pwm_out <= '0';          -- Output LOW
    end if;
  end process;

end Behavioral;


--Pwm_isnt: entity PWM
--  Port map (
--    ck      => ,
--    cmpPwm  => ,
--    pwm_out =>
--  );
